Uvod
As an EDA Methodology Engineer, you will play a pivotal role in developing and enhancing ASIC design flows using Synopsys Design Compiler. You’ll collaborate closely with design teams and tool vendors to deliver robust, scalable, and efficient synthesis methodologies that power IBM’s cutting-edge microprocessor chips.
Vaša vloga in odgovornosti
- Design and implement synthesis flows using Synopsys Design Compiler.
- Collaborate with cross-functional teams to align methodology with design requirements.
- Drive innovation in SoC design methodologies, tools, and flows.
- Provide technical leadership and support to resolve RTL, DFT, and synthesis-related issues.
- Interface with EDA vendors to evaluate and integrate new tool features.
- Ensure methodology scalability and robustness across multiple projects.
Zahtevana izobrazba
Diploma prve stopnje
Zaželena izobrazba
Magisterij
Zahtevano strokovno in tehnično znanje
- Bachelor’s or Master’s degree in Computer Science, Electronics Engineering, or VLSI Design.
- 5–8 years of hands-on experience with Synopsys Design Compiler.
- Strong understanding of RTL design (VHDL, Verilog, System Verilog), physical design, and DFT.
- Proficiency in scripting languages such as Tcl and Python.
- Experience with incremental synthesis and custom flow development.
- Excellent debugging and problem-solving skills.
- Strong interpersonal and communication skills to work effectively across teams.
Zaželeno strokovno in tehnično znanje
- Deep familiarity with Synopsys Design Compiler and related synthesis tools.
- Prior experience in developing and deploying EDA methodologies in large-scale SoC projects.