Analog layout design requires knowledge of designing layout of complex VLSI (very large scale integration) circuits using graphic editing tools in Analog domain. A major portion of the job is in creation of new physical design data from concepts, partial schematics or a working knowledge of overall requirements. Responsibilities include checking the design integrity with respect to semiconductor ground rules and the logical function of the circuit. Symbolic circuit data (schematics) are converted to physical shapes which represent the semiconductor process. The role ranges from manual shapes and checking tool manipulations to extended team coordination and methodology creation. The employee guides functional objectives or technologies.
1. Hands on work on custom layout for analog blocks like High Speed SerDes and General purpose IO designs with Cadence Virtuoso on latest technologies like 5nm and below and also take leadership roles in delivery of IPs 2. Work on Floor planning, power design, signal routing strategy, EMIR awareness and parasitic optimisations
3. Understand and apply analog Layout techniques to ensure the design meets performance with minimum possible area and good yield.
4. Participate in building and enhancing layout flow for faster, higher quality design process.
5. Checking physical verifications like DRC/LVS/ERC/ANT/DFM and other IBM internal checks
6. Collaborate with Circuit Designers to solve challenging problems
7. Writing SKILL/PYTHON scripts to automate repetitive tasks
8. Work with Place and Route engineer to integrate custom macros into top level.
9. Able to perform design reviews across global team
10. Work closely with required global teams to ensure the success of the whole product. 11. Leadership in delivery of macros we plan to own from India
Job requirements:
1. Experience in doing layouts for analog blocks like SerDes, ADCs, DACs, LDOs, PLLs, BGAP & amplifiers etc.
2. Experience in designing layouts for high-speed circuits is a plus.
3. Layout experience in the following technology nodes: 3nm, 5nm and 7nm FinFET.
4. Good team worker with multi-discipline, multi-cultural and multi-site environments
5. Strong fundamental knowledge in semiconductor device physics, layout principles, IC reliability and failure mechanisms
6. Good problem-solving skills are essential where problems are analysed upfront, identifying gaps, and providing optimum solutions
7. Knowledge in Skill/perl/tcl/Python scripting is a plus.
The Analog layout design engineer with experience in next generation Ultra high speed serial
IO link (HSS) interface for Cognitive, ML,DL, and data center applications. The engineer needs to have knowledge in the design and development full custom analog layouts for ultra high speed 32G/50G/112G IO link interfaces.
Experience in 7 and 14 nm analog layout design. Working on Cutting edge technology and HSS domain . Quick learner, deep layout design knowledge, problem solving skills and good communication skills with cross teams across the Geos.