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As a CPU Verification Engineer, you will be responsible for the pre-silicon functional and performance verification of our chipsets, covering the CPU core, cache/nest subsystem, memory hierarchy, and other on-silicon IP used in our next-generation IBM Power Systems and IBM Z Systems offerings. You will use state-of-the-art techniques to simulate and verify the designs of these custom microprocessor-based systems. The job uses both hardware and software engineering skills, and entails creating environments and methodologies for simulating the VHDL input, as well as analysis and problem debug. Verification is performed at various levels within the design hierarchy. A background in Computer Engineering or Electrical Engineering with strong programming skills is required.
•Functional Verification Experience: Extensive experience in functional verification of processors or ASICs, demonstrating a deep understanding of verification methodologies.
•Computer Architecture Knowledge: In-depth knowledge of computer architecture, including processor core design specifications, instruction set architecture, and logic verification.
•Multi-Processor Cache Coherency: Experience in verifying multi-processor cache coherency and memory subsystems, ensuring seamless operation in complex systems.
•Gate Level Simulation and Emulation: Proficiency in gate level simulation and emulation techniques, facilitating thorough verification of designs.
•Functional Verification Methodology: Expertise in functional verification methodologies such as UVM/OVM/System Verilog/SystemC, ensuring effective verification of designs.
•Advanced Verification Techniques: Familiarity with advanced verification techniques such as formal verification or assertion-based verification, enhancing verification thoroughness and efficiency.
•Experience with Hardware Description Languages (HDLs): Proficiency in hardware description languages like Verilog and VHDL, enabling seamless collaboration with design teams and enhancing verification effectiveness.
•Experience in System-Level Verification: Exposure to system-level verification methodologies and techniques, ensuring holistic verification coverage across multiple levels of design abstraction.