The hardware team in Boeblingen develops the most powerful server systems in the world – in an international work environment with our partner labs in the USA, Israel and India. We are using modern verification methods and are continuously optimizing our development processes.
We are offering an Master-Thesis: Enabling an open-source verification flow for IBM processors
Are you interested in software development with C++, open source, and how processor chips are made? Do you want to explore this area further in a Master’s Thesis at IBM?
At IBM we develop complex processor chips. Before the actual chip is produced we simulate the chip’s behavior using a software tool called “logic simulator”. For the majority of our work we use a high-speed in-house simulator. In the first part of this thesis you will be evaluating an alternative: the open source tool Verilator. Verilator has been around for a long time (in software terms) and has grown into a powerful and capable tool with a very active community. But does it also work for our chip designs, and in our environment?
A logic simulator alone is not enough to know if the processor chip will work after it has been produced. To do the testing we write a testbench, essentially a large C++ application that produces inputs for the simulation and checks the outputs against our expectations. In the second part of your thesis, your task is to connect our testbench framework with Verilator and evaluate this integration: does it work? how fast is it? what are the limitations?
This thesis will give you an insight into how the chips that power our world are created. You will be able to use and advance your software development skills, and strengthen your analytical skills when identifying and understanding software performance. Thankfully, you’re not alone: we are a friendly and international team that knows not only how to use tools, but also how to develop them. We are here to help you out when you’re stuck, to discuss your findings, and to celebrate your success.
If you’re interested please get in contact with us and include in your response all relevant documents (preferably all in one single pdf file):
- Cover Letter incl. your availability (earliest start and latest end date)
- CV incl. your level of German
- Certificate of enrollment from you university
- Current transcript of records and other relevant certificates / references
- Non-EU citizen studying in Germany: copy of passport, residence and work permit
- Non-EU citizen studying elsewhere: prove of identity incl. place of birth
We are looking forward to your application !
- Study of computer science, electrical engineering or a similar direction
- Both Verilator and our testbenches are written in C++, and both are reasonably large code bases. Prior experience with software development on more than toy projects will help you.
- Knowledge of Development tools / technologies (e.g. git)
- Strong abilities in communication in English
- Interest in chip design or first experience with Verilog
- Experience in software profiling methodologies and tools
- Experience in open-source projects