We are seeking a highly motivated Mask Release Automation Engineer to join
our cutting-edge IBM Research team focused on next-generation semiconductor test chip development. This cross-functional role bridges the gap between design automation and mask release operations, requiring a blend of software engineering skills and a foundational understanding of semiconductor layout and manufacturing. The successful candidate will drive
automation initiatives, streamline mask data processing flows, and coordinate end-to-end reticle delivery, ensuring precision and efficiency in support of aggressive tape-out schedules.
Key Responsibilities:
• Reticle Data Preparation: Prepare and manage reticle order documentation and post-process layout data using internal automation tools for timely submission to mask houses.
• Design Automation: Develop and deploy automation solutions to enhance test chip tape-out infrastructure and workflows, focusing on photomask release.
• Data Management & Traceability: Implement improvements in reticle data management systems, ensuring data traceability and compliance with lithographic tool requirements.
• Cross-Functional Coordination: Coordinate and lead cross-functional meetings with design, process, and mask house teams to validate and review mask data pre- and post-submission.
• Debugging and Problem-Solving: Troubleshoot layout data and automation issues in collaboration with infrastructure and design enablement teams.
• Agile Development: Optimize workflows using CI/CD tools such as Jenkins to improve throughput, reliability, and integration with cloud-based resources.
• Efficiency Improvements: Analyze and improve testsite execution efficiency through scripting, infrastructure upgrades, and enhanced automation
• Bachelor’s Degree in Computer Science, Computer Engineering, Electrical Engineering or related field with experience in VLSI chip development or semiconductor technology.
• Coding proficiency with software or scripting languages (C, C++, Python, Perl, etc) for automation purposes, with 2+ years of experience.
• Strong understanding of Linux environments and shell scripting with 2+ years of experience.
• Familiarity with physical semiconductor layout and technology ground rules.
• Demonstrated communication and collaboration skills to work effectively in cross-functional teams.
• Troubleshooting and problem-solving abilities in a collaborative environment.
Master’s in Electrical, Computer, Chemical, or Materials Science Engineering with 3+ years of experience.
• Advanced knowledge of Semiconductor Processes in one of the following domains: Process Design Kits, Design Enablement, Macro Design, Logic Technology, Patterning, OPC, Computational Lithography.
• Proven experience in developing automation solutions to enhance quality and runtime efficiency.
• Experience with version control systems such as Git and familiarity with collaborative software development workflows (e.g., GitHub, GitLab, or Bitbucket).
• Hands-on experience in mask tape-out operations & logistics, including mask data preparation, in-line metrology, OPC, and reticle frame building (3+ years).
• Proficiency with at least one EDA tool vendor (Synopsys ICWB, Cadence Virtuoso, Cadence MaskCompose) with 3+ years of design experience
• Familiarity with layout verification tools from Cadence, Synopsys, or Siemens, including design rule checking (DRC) with 5+ years of relevant experience.