Introduction
We are looking for a passionate and experienced EDA Methodology Engineer to join our ASIC design team, focusing on formal equivalence checking using Synopsys Formality. In this role, you’ll work closely with design teams and EDA vendors to develop and implement robust verification flows that ensure functional correctness across design stages.
Your role and responsibilities
- Develop and maintain formal equivalence checking flows using Synopsys Formality.
- Collaborate with cross-functional teams to align verification methodology with design goals.
- Implement and support Formality ECO flows for incremental synthesis.
- Drive methodology improvements for SoC design verification.
- Coordinate with internal stakeholders and external vendors to deliver high-quality solutions.
Required education
Bachelor's Degree
Preferred education
Master's Degree
Required technical and professional expertise
- Bachelor’s or Master’s degree in Computer Science, Electronics Engineering, or VLSI Design.
- 5–8 years of hands-on experience with Synopsys Formality or similar tools (e.g., Cadence Conformal LEC, JasperGold).
- Strong understanding of RTL design languages: VHDL, Verilog, SystemVerilog.
- Expertise in Tcl and Python scripting.
- Deep knowledge of logic synthesis and gate-level netlist verification.
- Experience in setting up and running equivalence checks between RTL and synthesized netlists.
- Proven ability to troubleshoot and resolve complex verification issues.
- Strong communication and collaboration skills.
Preferred technical and professional experience
- Experience with Formality ECO flows.
- Familiarity with formal verification methodologies in large-scale SoC projects.