As a Hardware at , you’ll get to work on the systems that are driving the quantum revolution and the AI era. Join an elite team of engineering professionals who enable customers to make better decisions quicker on the most trusted hardware platform in today’s market.
As Logic deisgn engineer for Power Management, you will be responsible for design and
development of power management and sustainability features for high
performance Processors chips.
1. Lead the Development of features - propose enhancements to existing
features, new features, architecture in High level design discussions
2. Develop micro-architecture, Design RTL, Collaborate with the Verification,
DFT, Physical design, FW, SW, Research teams to develop the feature
3. Guide junior engineers. Represent as Power engineer in various
forums.
4. Signoff the Pre-silicon Design that meets all the functional, area and timing
goals
5. Participate in silicon bring-up and validation of the hardwar
6. Estimate the overall effort to develop the feature and close design
3-8 years of work experience of one or more areas Power management Architecture/ microarchitecture/ Logic design – Deep technical understanding of dynamic power saving, power capping, droop mitigation techniques.
1. Experience of working on Power Management designs handling
Power/Performance States, Stop states of Core and Cache, Chip and System
thermal management and power supply current over-limit management
2. Experience in working with research, architecture/ FW/ OS teams
3. Experience in low power logic design
4. Experience in working with verification, validation for design closure including
test plan reviews, verification coverage
5. Good understanding of Physical Design, and able to collaborate with physical
design team for floor-planning, placement of blocks for achieving high-
performance design and timing closure of high frequency designs
6. Experience in silicon bring-up